Physical chip design has become a real challenge today. Now, more than ever, achieving timing convergence between physical design and logical design has become such an issue that EDA vendors, silicon vendors and end users alike are scrambling to obtain solutions that will at least allow them to get current designs into manufacturing.
In the past, the management of gate delay was the main concern to designers. Interconnect delay contributed such a small amount to the overall chip delay that it was either ignored or assumed to be negligible. Similarly, signal-integrity and quality issues such as crosstalk and electromigration were rarely a concern. Today, however, both chip performance and signal integrity are dictated by the interconnect topology. Even with copper interconnect and low-k dielectrics, interconnect contributes in excess of 45 percent of the total delay at 0.18 micron fabrication and below. With wires being taller, thinner and closer, coupling capacitance, a principle cause of crosstalk, is the dominant form of capacitance of which the designers must contend. No existing physical-design tools adequately address this issue.
Synthesis is usually the final step performed in front-end logic design. The output of synthesis is a gate-level net-list containing cells from the tool vendor's library chosen to meet the designer's functional and performance constraints. Cell selection and sizing are determined by using statistical wire-load models to "estimate" the actual interconnect loading that will exist in the physical layout. Those wire-load models are essentially random numbers that do not correlate well with the real delays due to interconnect and coupling capacitance. The actual interconnect load and resulting performance in the physical layout usually differ significantly from the prediction resulting from synthesis.
To solve the problem, some vendors are pushing RTL floor planning on the premise that predictions can be made early in the design process to provide better performance information than possible by doing full synthesis. One approach uses a concept of "logic effort" in an attempt to achieve an accurate estimate of the gate delay. The theory of logical effort represents the delay D.sup.gate through a simple logic gate, driving a capacitive load as: EQU D.sub.gate =.tau.(g.sub.gate h.sub.gate +p.sub.gate)
where g.sub.gate is the logical effort of the gate, h.sub.gate is the electrical effort of the gate, and p.sub.gate is the intrinsic delay of the gate. The Greek letter .tau. is a technology constant defined as the delay of an ideal inverter with no intrinsic delay, driving another ideal inverter.
The logical effort g.sub.gate represents the computational complexity of the gate and measures how much weaker it is in current drive compared to an ideal inverter with the same input capacitance. Logical effort compares the characteristic time constant (i.e., the product of the output resistance and input capacitance) of a gate with that of an inverter. Logical effort is a function of the topology of the transistor interconnections, but not of transistor sizes and is given by: ##EQU1##
where gate_min refers to the minimum sized gate and inv_min to the minimum sized inverter.
The electrical effort h.sub.gate is the ratio of the load capacitance to input capacitance and does depend on the transistor sizes. Electrical effort h.sub.gate is given by: ##EQU2##
where C.sub.load is the load capacitance of the gate in the given network, and C.sub.in the input capacitance.
The parasitic delay p.sub.gate occurs primarily due to source/drain diffusion capacitance C.sub.diff.sub..sub.-- .sub.min at the output of the minimum sized gate. The parasitic delay depends on the layout geometry, but is independent of the sizes. ##EQU3##
For more information on logical effort, see I. E. Sutherland, R. F. Sproull, and D. Harris, "Logical Effort: Designing Fast CMOS Circuits," Morgan Kaufman Publishers, 1999.
Some other approaches to the problem include using parallel computing in an attempt to reduce the time required for each iteration in the design process. More processing power by itself is not likely to fix the problem. Therefore, designers do not have adequate tools available to them to try to obtain timing convergence.